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- Cadence® Simulation Analysis Environment (SimVision)
- Verifault – XL Simulator
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- Enterprise Simulator – XL Interface for MTI
- Enterprise Simulator – XL Interface for VCS
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- Incisive™ Enterprise Verifier – XL
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- Virtuoso® AMS Designer Verification Option
Verification Process Automation
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Pre-verified, Re-usable Verification IP Components
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A few helpful commands:
The verilog executable is used to start the Cadence Verilog software as well as DAI Signalscan Waveform , Signal Flow Browser and Cadence Navigator.
The analyzer, ncvhdl, encapsulates two tools : the VHDL parser and the code generator. The parser performs syntactic and static semantic checking on the input source files. If no errors are found, compilation produces an internal representation for each HDL design unit in the source files. These intermediate objects are stored in a library directory.
The elaborator, ncelab, constructs a design hierarchy based on the instantiation and configuration information in the design, establishing signal connectivity, and computes initial values for all objects in the design. The elaborated design hierarchy is stored in a simulation snapshot file, which is used by the simulator.
In order to use this, the files cds.lib and hdl.var must be in the same directory that you typed ncvhdl (usually your home directory).
SOFTINCLUDE $LDV_DIR/inca/files/cds.lib DEFINE worklib ./worklib
SOFTINCLUDE $LDV_DIR/inca/files/hdl.var DEFINE USE_NEW_SIMWAVE_WINDOW ON DEFINE EDITOR vi DEFINE CDS_TEXT_EDITOR vi DEFINE WORK worklib