Cadence Verification Bundle

Functional Verification

  • Incisive Enterprise Simulator – L
  • Cadence® Simulation Analysis Environment (SimVision)
  • Verifault – XL Simulator
  • Incisive™ Enterprise Simulator
  • Enterprise Simulator – XL Interface for MTI
  • Enterprise Simulator – XL Interface for VCS
  • Incisive™ Formal Verifier
  • Incisive™ Enterprise Verifier – XL
  • Incisive™ Software Extension
  • Virtuoso® AMS Designer Verification Option

Verification Process Automation

  • Incisive™ Enterprise Manager

Pre-verified, Re-usable Verification IP Components

  • Incisive™ VIP Portfolio


A few helpful commands:

Command Description
verilog Verilog-XL

The verilog executable is used to start the Cadence Verilog software as well as DAI Signalscan Waveform , Signal Flow Browser and Cadence Navigator.

Command Description
ncvhdl Analyzer
ncelab Elaborator
ncsim Affirma NC-Simulator

The analyzer, ncvhdl, encapsulates two tools : the VHDL parser and the code generator. The parser performs syntactic and static semantic checking on the input source files. If no errors are found, compilation produces an internal representation for each HDL design unit in the source files. These intermediate objects are stored in a library directory.

The elaborator, ncelab, constructs a design hierarchy based on the instantiation and configuration information in the design, establishing signal connectivity, and computes initial values for all objects in the design. The elaborated design hierarchy is stored in a simulation snapshot file, which is used by the simulator.

In order to use this, the files cds.lib and hdl.var must be in the same directory that you typed ncvhdl (usually your home directory).

cds.lib example
SOFTINCLUDE $LDV_DIR/inca/files/cds.lib

DEFINE worklib ./worklib
hdl.var example
SOFTINCLUDE $LDV_DIR/inca/files/hdl.var