Cadence

Cadence Digital Integrated Circuits Bundle

Place & Route and Timing

  • Virtuoso® Layout Suite – GXL
  • Cadence® Chip Assembly Router

Physical Verification

  • Dracula® Physical Verification and Extractor Suite

Design for Manufacturing

  • Virtuoso® QRC Extraction – L
  • VoltageStorm (transistor)
  • Encounter Power System – L

Signal Integrity

  • Encounter™ Timing System – XL
  • PacifIC Static Noise Analyzer for Custom Digital ICs
  • Encounter™ Timing System – L
  • Encounter™ Library Characterizer – XL

Silicon Virtual Prototyping

  • Encounter™ Digital Implementation System – XL
  • Encounter™ Low Power GXL Option
  • Encounter™ Advanced Node GXL Option

Test

  • Architect Advanced Option to RC
  • Encounter™ True Time Test Advanced
  • Encounter™ Diagnostics Engine – XL

Digital System-In-Product (SIP)

  • Cadence® SiP Digital Architect – GXL
  • Cadence® SiP Digital SI – XL
  • Cadence® Chip Integration Option

Formal Verification

  • Encounter™ Conformal – GXL

Synthesis

  • Encounter™ RTL Compiler – XL
  • Encounter™ RTL Compiler – GXL option
  • Encounter™ RTL Compiler with physical

Chip Planning

  • Cadence® InCyte Chip Estimator L
  • Cadence® InCyte Chip Estimator XL