Department of Electrical Engineering
B.S.E.E., Oklahoma State University, 1985; M.S.E.E., University of Texas at Arlington, 1990; M.S.C.S. Southern Methodist Univeristy, 1993; Ph.D., Computer Engineering, Southern Methodist University
Reversible Logic Synthesis Based on Decision Diagram Variable Ordering, Journal of Multiple-Valued Logic and Soft Computing, (to appear, with D.Y. Feinstein).
To PE or not to PE ... The Sequel, IEEE Computing in Science and Engineering, IEEE Computer Society Press and American Institute of Physics, July/August 2010, vol. 12, no. 4, pp. 62-65, (with Steven F. Barrett).
Minimization of Quantum Multiple-Valued Decision Diagrams using Data Structure Metrics, Journal of Multiple-Valued Logic and Soft Computing, vol. 15, no. 4, pp. 361-377, (with D.Y. Feinstein and D.M. Miller).
A Redundant Signed Binary Addition Based Digital-to-Frequency Converter, IEE Electronics Letters, vol. 45, no. 2, pp. 824-826, July 2009, (with W. Chen and P. Gui).
A Discrete Logarithm Number System for Integer Arithmetic Modulo 2k: Algorithms and Lookup Structures, IEEE Transactions on Computers, vol. 58, no. 2, Feb. 2009, pp. 163-174, (with A. Fit-Florea, L. Li, and D.W. Matula).
A Methodology for Disaster Tolerance Utilizing the Concepts of Axiomatic Design, IIIS Journal of Systemics, Cybernetics and Informatics, vol. 6, no. 4, 2008, (with D. Easton, V.S.S. Nair, and S.A. Szygenda).
Components of Disaster Tolerant Computing: Analysis of Disaster Recovery, IT Application Downtime & Executve Visibility, International Journal of Business Information Systems,vol. 3, no. 3, 2008, pp. 317-331, (with C.M. Lawler, M.A. Harper, and S.A. Szygenda).
QMDD Minimization using Sifting for Variable Reordering, Journal of Multiple-Valued Logic and Soft Computing, vol. 13, no. 4-6, 2007, pp. 537-552, (with D.M. Miller and D.Y. Feinstein).
Integrated Design Validation: Combining Simulation and Formal Verification in Integrated Circuit Design, IIIS Journal of Systemics, Cybernetics and Informatics, vol. 4, no. 2, 2006, (with L. Li and S. Szygenda).
A Coarse-Grain Phased Logic CPU, IEEE Transactions on Computers, vol. 54, no. 7, July 2005, pp. 788-799, (with R. B. Reese and C. Traver).
Early Evaluation for Performance Enhancement in Phased Logic, IEEE Transactions on Computer Aided Design, (vol. 24, no. 4, pp. 532-550, April 2005, (with R. B. Reese, C. Traver, and D. Hemmendinger).
Additive Bit-serial Algorithm for the Discrete Logarithm Modulo 2k, IEE Electronics Letters, vol. 41, no. 2, pp. 57-59, January 2005, (with A. Fit-Florea and D.W. Matula).
Addition-based Exponentiation Modulo 2k, IEE Electronics Letters, vol. 41, no. 2, pp. 56-57, January 2005, ( with A. Fit-Florea and D.W. Matula).
Computation of Discrete Function Chrestenson Spectrum Using Cayley Color Graphs, Journal of Multiple-Valued Logic and Soft Computing, vol. 10, no. 2, 2004, pp. 189-202, (with D. Michael Miller).