Department of Computer Science and Engineering

Theodore Manikas, P.E.

Lecturer

B.S., Electrical Engineering, Michigan State University; M.S., Electrical Engineering, Washington University; Ph.D., University of Pittsburgh

214-768-3083
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Research

* Computer engineering * VLSI and nanotechnology circuit design * Genetic algorithms * Computer-aided design methods * Autonomous robot navigation


Publications

  1. "A Genetic Algorithm for Autonomous Navigation Using Variable-Monotone Paths", K. H-Sedighi, K. Ashenayi, T.W. Manikas, and R.L. Wainwright, Int. Journal of Robotics and Automation, accepted for publication.
  2. "An Electrical Engineering Summer Academy for Middle School and High School Students", P. LoPresti, T.W. Manikas, and J. Kohlbeck, IEEE Transactions on Education, accepted for publication.
  3. "COOLER- A Fast Multiobjective Fixed-outline Thermal Floorplanner", D. Chatterjee, T.W. Manikas, I. Markov, Proc. 3rd Annual Austin Conf. on Integrated Systems & Circuits (ACISC-08), 2008.
  4. "Nanobattery-crossbar system, a promising candidate for future nanoscale data storage", P.C. Utekar, T.W. Manikas, and D. Teeters, Proc. 213th ECS (ElectroChemical Society) Meeting, 2008.
  5. "Multiple-Valued Logic Memory System Design Using Nanoscale Electrochemical Cells", T.W. Manikas and D. Teeters, Proc 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL-08), 2008, pp. 197-201.
  6. "Genetic Algorithms for Autonomous Robot Navigation", T.W. Manikas, K. Ashenayi, and R.L. Wainwright, IEEE Instrumentation & Measurement Magazine, vol. 10, no. 6, Dec. 2007, pp. 26-31 (invited paper).
  7. "A Genetic Algorithm for Non-Slicing Floorplan Representation", D. Chatterjee and T.W. Manikas, Proc. Nat. Conf. on Intelligent Systems (NCIS), 2007.
  8. "Nanoscale Power and Memory Unit Design for Nanoscale Sensor Systems", T.W. Manikas and D. Teeters, Proc. 53rd ISA Int. Instrumentation Symp., 2007.
  9. "Power-Density Aware Floorplanning for Reducing Maximum On-Chip Temperature", D. Chatterjee and T.W. Manikas, Proc. 18th IASTED Int. Conf. on Modelling and Simulation, 2007.
  10. “Evolving A Diverse Collection of Robot Path Planning Problems”, D. Ashlock, T.W. Manikas, and K. Ashenayi, Proc. 2006 IEEE Congress on Evolutionary Computation, 2006.
  11. “Benchmarking of Robot Path Planning Algorithms”, A. Hand, J. Godugu, K. Ashenayi, T.W. Manikas, and R.L. Wainwright, in Intelligent Engineering Systems Through Artificial Neural Networks: Smart Engineering Systems Design: Neural Networks, Fuzzy Logic, Evolutionary Programming, Complex Systems and Artificial Life, C.H. Dagli, et al., Editors. Vol. 15, 2005, ASME Press: New York.
  12. “Autonomous Robot Navigation Using a Genetic Algorithm with an Efficient Genotype Structure”, A. Hermanu, T.W. Manikas, K. Ashenayi, and R.L. Wainwright, in Intelligent Engineering Systems Through Artificial Neural Networks: Smart Engineering Systems Design: Neural Networks, Fuzzy Logic, Evolutionary Programming, Complex Systems and Artificial Life, C.H. Dagli, et al., Editors. Vol. 14, 2004, ASME Press: New York. p. 319-324.
  13. "Autonomous Local Path Planning for a Mobile Robot Using a Genetic Algorithm", K. H-Sedighi, K. Ashenayi, T.W. Manikas, R.L. Wainwright, H.M. Tai, Proc. 2004 IEEE Congress on Evolutionary Computation, 2004.
  14. "A Genetic Algorithm for Mixed Macro and Standard Cell Placement", T.W. Manikas and M.H. Mickle, Proceedings of the 45th IEEE International Midwest Symposium on Circuits and Systems, 2002.
  15. "Autonomous Robot Navigation System Using a Novel Value Encoded Genetic Algorithm", T. Geisler and T.W. Manikas, Proceedings of the 45th IEEE International Midwest Symposium on Circuits and Systems, 2002.
  16. "Channel Height Estimation in VLSI Design", L. Li, T.W. Manikas, and H. Jin, Proceedings of the 45th IEEE International Midwest Symposium on Circuits and Systems, 2002.
  17. "Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement", T.W. Manikas and G.R. Kane, Proceedings of the 11th IEEE/ACM International Workshop on Logic and Synthesis, 2002.
  18. "Standard Cell Partition Size Variance and its Effect on Physical Design", T.W. Manikas and G.R. Kane, Proceedings of the 10th IEEE International Workshop on Logic and Synthesis, 2001.