Jennifer Dworak

Contact Information

Education

B.S.E.E.,Texas A&M University, 1998; M.S.E.E., Texas A&M University, 2000; Ph.D. in Electrical Engineering, Texas A&M University, 2004.

Publications

• M. R. Grimaila, S. Lee, J. Dworak, K. M. Butler, B. Stewart, H. Balachandran, B. Houchins, V. Mathur, J. Park, L-C. Wang, and M. R. Mercer, "REDO -- Random Excitation and Deterministic Observation -- First Commercial Experiment," Proc. 1999 IEEE VLSI Test Symposium, Dana Point, CA., April 25 - 29, 1999, pp. 268-274. (Best Paper Award at 1999 VLSI Test Symposium)
• J. Dworak, M. R. Grimaila, S. Lee, L-C. Wang, and M. R. Mercer, "Modeling the Probability of Defect Excitation for a Commercial IC with Implications for Stuck-at Fault-Based ATPG Strategies," Proc. 1999 International Test Conference, Atlantic City, NJ, September 28 - 30, 1999, pp. 1031-1037.
• J. Dworak, M. R. Grimaila, S. Lee, L-C. Wang, and M. R. Mercer, "Enhanced DO-RE-ME Based Defect Level Prediction Using Defect Site Aggregation – MPG-D," Proc. 2000 International Test Conference, Atlantic City, NJ, October 3 - 5, 2000, pp. 930-939.
• J. Dworak, M. R. Grimaila, B. Cobb, T-C. Wang, Li-C. Wang, and M. R. Mercer “On the Superiority of DO-REME/ MPG-D Over Stuck-at-Based Defective Part Level Prediction,” Proceedings of the Ninth Asian Test Symposium, Taipei, Taiwan, December 4-6, 2000, pp. 151-157.
• J. Dworak, J. D. Wicker, S. Lee, M. R. Grimaila, K. M. Butler, B. Stewart, L-C. Wang, and M. R. Mercer, "Defect-Oriented Testing and Defective-Part-Level Prediction," IEEE Design and Test of Computers, January- February, 2001, Vol. 18, No. 1, pp. 31 - 41. (Chosen for reprinting in the Special Report Compiled by the Editors of IEEE Design and Test in 2002)
• S. Lee, B. Cobb, J. Dworak, M. R. Grimaila, and M. R. Mercer, “A New ATPG Algorithm to Limit Test Set Size and Achieve Multiple Detections of All Faults.” Proceedings of the 2002 Design, Automation, and Test in Europe Conference and Exhibition, Paris, France, March 4 - 8, 2002, pp. 94 - 99
• J.-J. Liou, L.-C. Wang, K.-T. Cheng, J. Dworak, M. R. Mercer, R. Kapur, and T. W. Williams, “Enhancing Test Efficiency for Delay Fault Testing Using Multiple-Clocked Schemes,” Proceedings of the 39th Design Automation Conference, New Orleans, LA, June 10 - 14, 2002, pp. 371 - 374.
• J.-J. Liou, L.-C. Wang, K.-T. Cheng, J. Dworak, M. R. Mercer, R. Kapur, and T. W. Williams, “Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme,” Proc. 2002 International Test Conference, Baltimore, MD, October 8 - 10, 2002, pp. 407 - 416.
• J. Dworak, J. Wingfield, B. Cobb, S. Lee, L.-C. Wang, and M. R. Mercer, “Fortuitous Detection and its Impact on Test Set Size Using Stuck-at and Transition Faults,” Proc. 2002 Defect and Fault Tolerance in VLSI Systems Symposium, Vancouver, Canada, November 6 - 8, 2002., pp. 177 - 185.
• J. Wingfield, J. Dworak, and M.R. Mercer, “Function-Based Dynamic Compaction and its Impact on Test Set Sizes,” Proc 18th International Symposium on Defect and Fault Tolerance in VLSI Systems, Cambridge, Massachusetts, November 3-5, 2003, pp. 167-174.
• J. Dworak, B. Cobb, J. Wingfield, and M.R. Mercer, “Balanced Excitation and its Effect on the Fortuitous Detection of Dynamic Defects,” Proc. of the 2004 Design, Automation, and Test in Europe Conference and Exhibition (DATE 2004), Paris, France, February 16-20, 2004, pp. 1066-1071. (181 papers were chosen from 702 submitted to the main technical tracks.)
• J. Dworak, D. Dorsey, A. Wang, and M.R. Mercer, “Excitation, Observation, and ELF-MD: Optimization Criteria for High Quality Test Sets,” Proceedings of the 2004 IEEE VLSI Test Symposium (VTS’04), Napa Valley, California, April 25-29, 2004, pp. 9-15. (TTTC Naveena Nagi Award)
• J. Dworak, J. Wingfield, and M. R. Mercer, “A Preliminary Investigation of Observation Diversity for Enhancing Fortuitous Detection of Defects,” Proc. 19th International Symposium on Defect and Fault Tolerance inVLSI Systems, Cannes, France, October 11-13, 2004, pp. 460-468.
• V. Stojanovic, R. I. Bahar, J. Dworak, and R. Weiss, “Instruction Queue Based Transient Error Identification and Correction through Cost Effective Hardware ECC,” HPCRI: 2nd Workshop on High Performance Computing Reliability Issues, (held in conjunction with HPCA: Symposium on High Performance Computer Architecture), 2006
• V. Stojanovic, R. I. Bahar, J. Dworak, and R. Weiss, “A Cost-Effective Implementation of an ECC-Protected Instruction Queue for Out-of-Order Microprocessors,” Proceedings of the 43rd IEEE/ACM Design Automation Conference, July 24-28, 2006, pp. 705-708. (~20% acceptance rate)
• J. Dworak, "An Analysis of Defect Detection for Weighted Random Patterns Generated with Observation/Excitation-Aware Partial Fault Targeting," Proceedings of the 25th VLSI Test Symposium, May 6-10, 2007 pp. 205-210. (~35% acceptance rate).
• J. Dworak “Which Defects Are Most Critical? Optimizing Test Sets to Minimize Failures due to Test Escapes,” Proceedings of the 2007 IEEE International Test Conference (ITC’07), Santa Clara, California, October 23-25, 2007.
• E. Alpaslan, Y. Huang, X. Lin, W-T Cheng, and J. Dworak, “Reducing Scan Shift Power at RTL,”Proceedings of the 26th VLSI Test Symposium (VTS’08), pp. 139-146, April 27-May 1, 2008., pp. 139-146, April 27-May 1, 2008.
• Y. Shi, K. DiPalma, and J. Dworak, “Efficient Determination of Fault Criticality for Manufacturing Test Set Optimization,” Proceedings of the 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'08), October 1-3, 2008.
• K. Nepal, N. Alves, J. Dworak, and R. I. Bahar “Using Implications for Online Error Detection,” Proceedings of the 2008 IEEE International Test Conference (ITC’08), October 28-30, 2008. (CDROM proceedings)
• N. Alves, K. Nepal, J. Dworak, R. I. Bahar, “Detecting Errors using Multi-cycle Invariance Information” 2009 Design, Automation & Test in Europe Conference & Exhibition (DATE) April 20-24, 2009 in Nice, France.
• N. Alves, K. Nepal, J. Dworak, and R. I. Bahar, “Compacting Test Vector Sets via Strategic Use of Implications,” IEEE/ACM International Conference on Computer Aided Design, November 2009.
• E. Alpaslan, B. Kruseman, A. K. Majhi, W. Heuvalman, P. van de Wiel, and J. Dworak, “NIM- A Noise Index Model to Estimate Delay Discrepancies between Silicon and Simulation,” accepted for publication at 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE), to be held in Dresden, Germany, March 8-12, 2010.
• Y. Shi, W-C. Hu, and J. Dworak, “Too Many Faults, Too Little Time: On Creating Test Sets for Enhanced Detection of Highly Critical Faults and Defects” Proceedings of the 2010 VLSI Test Symposium (VTS 2010), Santa Cruz, California, April 18-21, 2010.
• N. Alves, A. Buben, K. Nepal, J. Dworak, and R. I. Bahar, “A Cost Effective Approach for Online Error Detection Using Invariant Relationships,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, issue 5, May 2010 ,pp. 788-801
• E. Alpaslan, Y. Huang, X. Lin, Wu-Tung Cheng, and J. Dworak “On Reducing Scan Shift Activity at RTL” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, issue 7, July vol. 29, issue 7, July 2010, pp. 1110-1120.
• N. Alves, K. Nepal, J. Dworak and R. I. Bahar, “Improving the Testability and Reliability of Sequential Circuits with Invariant Logic” GLSVLSI 2010 Proceedings, Great Lakes Symposium on VLSI, May 16-18, 2010.

• Best Paper Award, VLSI Test Symposium, Dana Point, CA, 1999
• National Science Foundation Graduate Research Fellowship, 2000 - 2003
• Best Student Presentation Award, International Test Synthesis Workshop, March 2002
• TTTC Naveena Nagi Award presented at the 2004 VLSI Test Symposium, April 2004

• Best Presentation in Section, University Undergraduate Fellow, 1997-1998
• The Association of Former Students & the Office of Graduate Studies Distinguished Graduate Student Award, Texas A&M University, 2000
• Ethel Ashworth-Tsutsui Memorial Award for Research, 2002 (generally one or two female Texas A&M graduate students chosen per year)

• Texas A&M University President’s Endowed Scholarship, 1994-1998
• Conrad and Marcel Schlumberger Scholarship, 1994-1998
• Ebensberger Graduate Fellowship in the Department of Electrical Engineering, 1999
• College of Engineering Fellowship in the Department of Electrical Engineering, 1999
• Fouraker Graduate Fellowship in the Department of Electrical Engineering, 2000
• Computer Engineering Scholarship for the Retention of Outstanding Graduates in the Department of Electrical Engineering, 2000
• Computer Engineering Fellowship for Excellent Doctoral Students in the Department of Electrical Engineering, 2003-2004

• Institute of Electrical and Electronics Engineers (IEEE)
• IEEE Computer Society
• Association for Computing Machinery (ACM)
• Tau Beta Pi Engineering Honor Society
• Eta Kappa Nu Electrical Engineering Honor Society
• Sigma Xi Honor Society
• Phi Kappa Phi Honor Society

Grants

Current Grants:

• National Science Foundation Grant in the area of Computer & Communication Foundations entitled: “SHF: Small: Collaborative Research: Using Identified Circuit Invariance of Online Error Detection", Award #: CCF-0915302. PI: Jennifer L. Dworak. Co-PI: Iris Bahar of Brown University. Award Date: September 2009. This is a collaborative grant with Kundan Nepal, an assistant professor at Bucknell University. The total amount of the grant at Brown is $411,614, with an additional ~$65K going to Bucknell.
• National Science Foundation Grant in the area of Computer & Communication Foundations entitled: “CAREER: Enhancing Quality through Probabilistic On-Chip Test.” PI: Jennifer L. Dworak. The total amount of the grant is $400K.

Completed Grants:

• Design Automation Conference Graduate Scholarship to support the project “A Statistical Coverage Metric and Stimulus Generation Approach for Design Verification Based upon Structural Analysis of the Design and Stimulus,” Awarded July 25, 2006 for one year, $24,000. Scholarship awarded for support of Elif Alpaslan in this project under my supervision.
• Equipment donation by Intel Corporation in support of projects in VLSI Computer-Aided Design. This generous Dworak, p. 8 gift consists of 6 workstations valued at approximately $18,123. Received April 2006. Principal Investigator: Jennifer Dworak.
• 2007 Salomon Award for the project: "An Investigation of Pattern-Limited Test Sets for the Detection of Errors Caused by Random Defects, Systematic Defects, and Process Variations," Awarded December 2006 with one year of funding beginning January 2007, $15,000. Principal Investigator: Jennifer Dworak.
• Career Development Award: Award to Jennifer Dworak and Iris Bahar at Brown University to provide funding to explore a research collaboration at the University of Bologna. June 1, 2007-December 31, 2008. $8,685 Principal Investigators: Jennifer Dworak and Iris Bahar.